This invention relates to a circuit for limiting the maximum current to be supplied to a load from a power MOS, in particular a current which is regulated by means of an equalizing capacitor.
Specifically, the invention concerns a circuit for limiting the maximum current to be supplied to a load from a power MOS, where the load is connected to a terminal of an external voltage supply and to the drain terminal of said power MOS, the circuit being of a type which comprises:
a current generator connected to the gate terminal of the power MOS, PA1 a resistance connected to the source terminal of the power MOS and to the ground terminal, PA1 an amplifier which consists of, PA1 an input stage comprising a pair of transistors whose collectors are connected to the output terminals of a current mirror circuit, and whose bases are connected to each other through a series of two resistances having the same value, the emitter of the first transistor being connected to the ground terminal, the emitter of the second transistor being connected to the source terminal of the power MOS, and the terminal shared in common by said resistances of equal value being connected to a terminal of a voltage reference, PA1 an output stage comprising a bipolar transistor of the pnp type having its emitter connected to the gate terminal of said power MOS, collector connected to ground, and base connected to the collector of the first of said pair of input stage transistors, and PA1 an equalizing capacitance connected between the collector and the base of the first of said input stage transistors of said amplifier.
There are several ways of limiting the current rating to a load through an output terminal of a power MOS. The most widely used one in the art uses a feedback network which comprises an amplifier having one input connected to a reference voltage, the other input connected to a resistor which senses the current being flowed through the load, and the output connected to the gate terminal of the power MOS.
That amplifier basically performs a comparison between the reference voltage and that applied to the other of its inputs which increases with the current across the load. As these two voltages tend to equal each other, the amplifier operates by its output to limit the voltage at the gate of the power MOS, thereby also limiting the current at the output terminal connected to the load.
A major problem to be addressed in such negatively fed back arrangements is that of stability, especially where the connected load is of the inductive type. In fact, the power MOS would tend to enter oscillation as soon as the amplifier is operated.
To obviate this drawback, the prior art has provided an equalizing capacitor in the circuit structure of the amplifier which is designed to stabilize the overall arrangement.
The introduction of that capacitor delays, however, the amplifier intervention, i.e. the limiting action on the load current, until the capacitor is fully charged. In the meantime, the load current may well rise above its desired strength with nothing to limit it. This particularly holds if the intrinsic input capacitance of the power MOS becomes charged ahead of the equalizing capacitor. In fact, since any MOS is bound to possess a certain input capacitance, its gate voltage, and hence its output current, would increase according to a time constant which is effectively tied to that input capacitance. Should the equalizing capacitor become charged at a slower rate, there would be a time period when the output current from the power MOS is no longer controlled. This may result in load current overshooting, that is load current values which exceed the rated value that the limiter circuit is to maintain.
Another factor which may practically defeat an accurate and effective limitation of the output current from a power MOS is the uncertainty of its (output) characteristic slopes due to manufacture processing (process spread) and to temperature variations (thermal drift).
The manufacturing processes frequently result in an actual device whose effective characteristic slopes depart from the theoretical ones set by its designer.
This means, for example, that if a given potential difference Vgs is applied between the source and the gate terminals, the current Id at the drain terminal will not be as expected, i.e. as inferable from the characteristic output slopes supplied by the manufacturer, and rather have a slightly different value. Thus, the MOS might fail to go on, or operate within the resistive range. Likewise, temperature variations from the design working value bring about changes in the characteristic slopes of the MOS which may perturb its expected performance. The above factors alter the operating conditions of the limiter circuit for the output current of a power MOS from those anticipated at the designing stage, which are based essentially on theoretical characteristic slopes. This may again result in inaccurate and/or untimely action of the limiter circuit, thereby dwarfing the benefits that the latter could bring about for the overall supply circuit of a load.
The disclosed innovations advantageously provide a circuit for limiting the maximum current to be supplied to a load through a power MOS, in particular a circuit which uses an equalizing capacitor, wherein the equalizing capacitor is charged at a faster rate than the intrinsic capacitance of the power MOS, so that it can intervene before the current at the load exceeds the maximum desired value.
The disclosed innovations advantageously provide a circuit as specified above, which is unaffected by process spreads and thermal drifts of the power MOS, such as would otherwise make its limiting action inaccurate and/or untimely.